WDTEN=0, TZFEN=0, IWDTEN=0, LVD2EN=0, RECCEN=0, RPEEN=0, OSTEN=0, LVD1EN=0, NMIEN=0, BUSMEN=0
Non-Maskable Interrupt Enable Register
| IWDTEN | IWDT Underflow/Refresh Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| WDTEN | WDT Underflow/Refresh Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| LVD1EN | Voltage monitor 1 Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| LVD2EN | Voltage monitor 2 Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| OSTEN | Main Clock Oscillation Stop Detection Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| NMIEN | NMI Pin Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| RPEEN | SRAM Parity Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| RECCEN | SRAM ECC Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| BUSMEN | Bus Master MPU Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| TZFEN | 0 (0): Disabled 1 (1): Enabled |